Electron transport in indium arsenide nanowires

The vapor–liquid–solid growth of semiconductor nanowires led to the implementation of engineered electronic and optoelectronic one-dimensional nanostructures with outstanding promise for device applications. To realize this promise, detailed understanding and control over their growth, crystal structure, and transport properties and their combined impact on device performance is vital. Here, we review our work on electron transport in InAs nanowires in a variety of device schemes. First, we provide a brief introduction and historical perspective on growth and transport studies in InAs NWs. Second, we discuss and present experimental measurements of ballistic transport in InAs nanowires over ∼200 nm length scale, which indicates a large electron mean free path and correlates with the high electron mobility measured on similar nanowires. Third, we devise a device model that enables accurate estimation of transport coefficients from field-effect transistor measurements by taking into account patristic device components. We utilize this model to reveal the impact of surface states, diameter, lateral and vertical fields, as well as crystal structure, on electron transport and transport coefficient calculation. We show in these studies that electron transport in InAs nanowires is dominated by surface state effects that introduce measurement artifacts in parameter extraction, reduce electron mobility for smaller diameters, and degrade the subthreshold characteristics of transistors made of Zinc Blende InAs nanowires. This device model is also used for isolating vertical and lateral field effects on electron transport in nanowire transistor channels and explaining observed negative differential conductance and mobility degradation at high injection fields, which is supported by electro-thermal simulations and microstructure failure analysis. We adopt the concept of lack of inversion symmetry in polar III-V materials and the resultant spontaneous polarization charges perpendicular to the electron transport trajectory in twinned Wurtzite nanowires to explain compensation of surface charges for this type of nanowires and their enhanced subthreshold characteristics over transistors made of Zinc Blende ones. Fourth, we discuss the combined effects of surface states and field variations in InAs nanowire transistor channels to shed light on the local electrostatic behavior in 1D channels studied by scanning probe measurements. Fifth, we survey and benchmark results on nanowire transistor performance and demonstrate the superiority of InAs nanowires for high-on currents and high-speed applications. Finally, we implement a novel integration scheme for InAs nanowires on Si substrates that enables vertical alignment and electrical isolation between nanowires which is necessary for achieving multifunctional devices per single chip. (Some figures in this article are in colour only in the electronic version) 0268-1242/10/024004+20$30.00 1 © 2010 IOP Publishing Ltd Printed in the UK Semicond. Sci. Technol. 25 (2010) 024004 Topical Review